riscv64: add compile support
This patch is a basic enablement that supports riscv64 compile. We are working on adding vector optimizations with riscv64 rvv extensions, and will push the implementations later.
This commit is contained in:
Changsheng Wu
@@ -194,6 +194,25 @@ endif
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OBJCHK += tools/checkasm-aarch64.o
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endif
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# RISCV64 RVV optims
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ifeq ($(SYS_ARCH),RISCV64)
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ifneq ($(findstring HAVE_RVV 1, $(CONFIG)),)
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SRCASM_X =
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SRCS_X +=
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OBJASM +=
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ifneq ($(findstring HAVE_BITDEPTH8 1, $(CONFIG)),)
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OBJASM += $(SRCASM_X:%.S=%-8.o)
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endif
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ifneq ($(findstring HAVE_BITDEPTH10 1, $(CONFIG)),)
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OBJASM += $(SRCASM_X:%.S=%-10.o)
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endif
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OBJCHK +=
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endif
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endif
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# MSA optims
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ifeq ($(SYS_ARCH),MIPS)
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ifneq ($(findstring HAVE_MSA 1, $(CONFIG)),)
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@@ -99,6 +99,8 @@ const x264_cpu_name_t x264_cpu_names[] =
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{"I8MM", X264_CPU_I8MM},
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{"SVE", X264_CPU_SVE},
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{"SVE2", X264_CPU_SVE2},
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#elif ARCH_RISCV64
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{"RVV", X264_CPU_RVV},
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#elif ARCH_MIPS
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{"MSA", X264_CPU_MSA},
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#elif ARCH_LOONGARCH
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@@ -459,6 +461,28 @@ uint32_t x264_cpu_detect( void )
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return flags;
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}
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#elif HAVE_RISCV64
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#define HWCAP_RISCV64_RVV (1 << ('V' - 'A'))
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uint32_t x264_cpu_detect( void )
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{
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uint32_t flags = 0;
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#if HAVE_GETAUXVAL || HAVE_ELF_AUX_INFO
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unsigned long hwcap = x264_getauxval( AT_HWCAP );
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if ( hwcap & HWCAP_RISCV64_RVV )
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flags |= X264_CPU_RVV;
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#else
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#if HAVE_RVV
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flags |= X264_CPU_RVV;
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#endif
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#endif
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return flags;
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}
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#elif HAVE_AARCH64
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#if defined(__linux__) || HAVE_ELF_AUX_INFO
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Vendored
+3
@@ -882,6 +882,9 @@ EOF
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UNAME_MACHINE=aarch64_be
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echo ${UNAME_MACHINE}-unknown-linux-gnu
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exit ;;
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riscv64:Linux:*:*)
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echo ${UNAME_MACHINE}-unknown-linux-gnu
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exit ;;
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alpha:Linux:*:*)
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case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
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EV5) UNAME_MACHINE=alphaev5 ;;
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Vendored
+2
@@ -255,6 +255,7 @@ case $basic_machine in
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# Some are omitted here because they have special meanings below.
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1750a | 580 \
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| a29k \
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| riscv64 \
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| aarch64 | aarch64_be | arm64 \
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| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
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| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
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@@ -370,6 +371,7 @@ case $basic_machine in
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# Recognize the basic CPU types with company name.
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580-* \
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| a29k-* \
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| riscv64-* \
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| aarch64-* | aarch64_be-* | arm64*-* \
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| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
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| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
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@@ -426,6 +426,7 @@ CONFIG_HAVE="MALLOC_H ALTIVEC ALTIVEC_H MMX ARMV6 ARMV6T2 NEON AARCH64 BEOSTHREA
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MSA LSX MMAP WINRT VSX ARM_INLINE_ASM STRTOK_R CLOCK_GETTIME BITDEPTH8 BITDEPTH10 ELF_AUX_INFO GETAUXVAL \
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SYSCONF SYNC_FETCH_AND_ADD \
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DOTPROD I8MM SVE SVE2 \
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RISCV64 RVV \
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AS_ARCHEXT_DOTPROD_DIRECTIVE AS_ARCHEXT_I8MM_DIRECTIVE AS_ARCHEXT_SVE_DIRECTIVE AS_ARCHEXT_SVE2_DIRECTIVE"
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# parse options
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@@ -885,6 +886,12 @@ case $host_cpu in
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AS="${AS-${CC}}"
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fi
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;;
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riscv64)
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ARCH="RISCV64"
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stack_alignment=16
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AS="${AS-${CC}}"
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;;
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s390|s390x)
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ARCH="S390"
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;;
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@@ -1076,6 +1083,15 @@ if [ $asm = auto -a $ARCH = MIPS ] ; then
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fi
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fi
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if [ $asm = auto -a $ARCH = RISCV64 ] ; then
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define HAVE_RISCV64
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if cc_check '' '' '__asm__(".option arch, +v\n" "vsetvli t0, a0, e32, m1, ta, ma");' ; then
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define HAVE_RVV
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fi
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ASFLAGS="$ASFLAGS -c"
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fi
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if [ $asm = auto -a $ARCH = LOONGARCH ] ; then
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if cc_check '' '' '__asm__("xvadd.b $xr0, $xr1, $xr2");' ; then
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# Use HAVE_LSX as the base flag, compiler support LA SIMD(LSX and LASX)
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@@ -1750,7 +1766,7 @@ cat conftest.log >> config.log
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cat conftest.log
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[ "$SRCPATH" != "." ] && ln -sf ${SRCPATH}/Makefile ./Makefile
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mkdir -p common/{aarch64,arm,mips,ppc,x86,loongarch} encoder extras filters/video input output tools
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mkdir -p common/{aarch64,arm,mips,ppc,x86,loongarch,riscv64} encoder extras filters/video input output tools
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echo
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echo "You can run 'make' or 'make fprofiled' now."
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+12
-1
@@ -115,6 +115,8 @@ static inline uint32_t read_time(void)
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uint64_t b = 0;
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asm volatile( "mrs %0, pmccntr_el0" : "=r"(b) :: "memory" );
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a = b;
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#elif ARCH_RISCV64
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asm volatile( "rdtime %0" : "=r"(a) :: "memory" );
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#elif ARCH_MIPS
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asm volatile( "rdhwr %0, $2" : "=r"(a) :: "memory" );
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#elif ARCH_LOONGARCH
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@@ -220,6 +222,8 @@ static void print_bench(void)
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b->cpu&X264_CPU_DOTPROD ? "dotprod" :
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b->cpu&X264_CPU_NEON ? "neon" :
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b->cpu&X264_CPU_ARMV8 ? "armv8" :
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#elif ARCH_RISCV64
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b->cpu&X264_CPU_RVV ? "rvv" :
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#elif ARCH_MIPS
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b->cpu&X264_CPU_MSA ? "msa" :
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#elif ARCH_LOONGARCH
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@@ -276,6 +280,10 @@ intptr_t x264_checkasm_call_noneon( intptr_t (*func)(), int *ok, ... );
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intptr_t (*x264_checkasm_call)( intptr_t (*func)(), int *ok, ... ) = x264_checkasm_call_noneon;
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#endif
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#if ARCH_RISCV64
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intptr_t x264_checkasm_call( intptr_t (*func)(), int *ok, ... );
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#endif
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#if ARCH_LOONGARCH
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intptr_t x264_checkasm_call( intptr_t (*func)(), int *ok, ... );
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#endif
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@@ -3014,6 +3022,9 @@ static int check_all_flags( void )
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ret |= add_flags( &cpu0, &cpu1, X264_CPU_SVE2, buf );
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}
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#endif
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#elif ARCH_RISCV64
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if( cpu_detect & X264_CPU_RVV )
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ret |= add_flags( &cpu0, &cpu1, X264_CPU_RVV, "RVV" );
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#elif ARCH_MIPS
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if( cpu_detect & X264_CPU_MSA )
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ret |= add_flags( &cpu0, &cpu1, X264_CPU_MSA, "MSA" );
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@@ -3035,7 +3046,7 @@ REALIGN_STACK int main( int argc, char **argv )
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if( argc > 1 && !strncmp( argv[1], "--bench", 7 ) )
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{
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#if !ARCH_X86 && !ARCH_X86_64 && !ARCH_PPC && !ARCH_ARM && !ARCH_AARCH64 && !ARCH_MIPS && !ARCH_LOONGARCH
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#if !ARCH_X86 && !ARCH_X86_64 && !ARCH_PPC && !ARCH_ARM && !ARCH_AARCH64 && !ARCH_MIPS && !ARCH_LOONGARCH && !ARCH_RISCV64
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fprintf( stderr, "no --bench for your cpu until you port rdtsc\n" );
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return 1;
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#endif
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