riscv64/filmgrain: Implemented generate_grain_y for 8bpc in RVV
This commit is contained in:
Mohd Zaid
committed by
Jean-Baptiste Kempf
Jean-Baptiste Kempf
parent
b62f72fc26
commit
c150ba6c9b
@@ -417,6 +417,8 @@ fguv_ss_fn(444, 0, 0);
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#include "src/arm/filmgrain.h"
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#elif ARCH_X86
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#include "src/x86/filmgrain.h"
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#elif ARCH_RISCV
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#include "src/riscv/filmgrain.h"
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#endif
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#endif
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@@ -436,6 +438,8 @@ COLD void bitfn(dav1d_film_grain_dsp_init)(Dav1dFilmGrainDSPContext *const c) {
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film_grain_dsp_init_arm(c);
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#elif ARCH_X86
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film_grain_dsp_init_x86(c);
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#elif ARCH_RISCV
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film_grain_dsp_init_riscv(c);
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#endif
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#endif
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}
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@@ -277,6 +277,7 @@ if is_asm_enabled
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if dav1d_bitdepths.contains('8')
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libdav1d_sources += files(
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'riscv/64/cdef.S',
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'riscv/64/filmgrain.S',
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'riscv/64/ipred.S',
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'riscv/64/itx.S',
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'riscv/64/mc.S',
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@@ -286,6 +287,7 @@ if is_asm_enabled
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if dav1d_bitdepths.contains('16')
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libdav1d_sources += files(
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'riscv/64/cdef16.S',
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'riscv/64/filmgrain16.S',
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'riscv/64/ipred16.S',
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'riscv/64/mc16.S',
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)
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@@ -0,0 +1,250 @@
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/*
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* Copyright © 2026, VideoLAN and dav1d authors
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* Copyright © 2026, Mohd Zaid
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "src/riscv/asm.S"
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#include "src/riscv/asm-offsets.h"
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#define GRAIN_WIDTH 82
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#define GRAIN_HEIGHT 73
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function generate_grain_y_8bpc_rvv, export=1, ext="v,zba,zbb"
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lbu t1, FGD_GRAIN_SCALE_SHIFT(a1)
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lla a2, dav1d_gaussian_sequence
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lwu a5, FGD_SEED(a1)
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addi t1, t1, 4
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addi sp, sp, -256
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csrwi vxrm, 0
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li t2, GRAIN_HEIGHT
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0:
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li t3, GRAIN_WIDTH
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1:
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vsetvli t0, t3, e16, m8, ta, ma
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mv t6, t0
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mv a6, sp
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2:
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// get random number
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srliw t4, a5, 1
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xor t5, a5, t4
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srliw t4, a5, 3
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xor t5, t5, t4
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srliw t4, a5, 12
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xor t5, t5, t4
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andi t5, t5, 3
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srliw a5, a5, 2
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slli t5, t5, 14
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or a5, a5, t5
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// gaussian sequence [value]
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srliw t4, a5, 4
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andi t4, t4, 2047
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slli t4, t4, 1
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srliw a7, a5, 5
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andi a7, a7, 2047
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slli a7, a7, 17
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or t4, t4, a7
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// push data onto stack
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sw t4, 0(a6)
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addi a6, a6, 4
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addi t6, t6, -2
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bnez t6, 2b
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// round2 and store
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vsetvli zero, t0, e16, m8, ta, ma
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vle16.v v8, (sp)
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vloxei16.v v16, (a2), v8
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vsetvli zero, t0, e8, m4, ta, ma
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vnclip.wx v4, v16, t1
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vse8.v v4, (a0)
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add a0, a0, t0
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sub t3, t3, t0
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bnez t3, 1b
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addi t2, t2, -1
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bnez t2, 0b
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addi sp, sp, 256
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// AR FILTER
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3:
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li t0, GRAIN_WIDTH * GRAIN_HEIGHT
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sub a0, a0, t0
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lb t1, FGD_AR_COEFF_LAG(a1)
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beqz t1, 15f
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addi sp, sp, -512
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lbu t2, FGD_AR_COEFF_SHIFT(a1)
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addi t3, a1, FGD_AR_COEFFS_Y
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li t4, 3
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li a2, GRAIN_WIDTH
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// vector pre-sum (dy < 0 taps)
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4:
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li a1, GRAIN_HEIGHT
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bge t4, a1, 14f
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li a4, GRAIN_WIDTH - 6
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li t6, 3
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mv t0, sp
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5:
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vsetvli a1, a4, e8, m2, ta, ma
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vsetvli zero, zero, e32, m8, ta, ma
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vmv.v.i v24, 0
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sub a7, zero, t1
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mv a6, t3
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add a3, t4, a7
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mul a3, a3, a2
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add a3, a3, a0
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add a3, a3, t6
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vsetvli zero, zero, e16, m4, ta, ma
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6:
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bge a7, zero, 9f
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sub a5, zero, t1
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add a3, a3, a5
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// dx loop
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sub a5, zero, t1
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7:
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bgt a5, t1, 8f
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lb t5, 0(a6)
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addi a6, a6, 1
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vle8.v v16, (a3)
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addi a3, a3, 1
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vsext.vf2 v20, v16
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vwmacc.vx v24, t5, v20
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addi a5, a5, 1
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j 7b
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8:
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add a3, a3, a2
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sub a3, a3, t1
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addi a3, a3, -1
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addi a7, a7, 1
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j 6b
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9:
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vsetvli zero, a1, e32, m8, ta, ma
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vse32.v v24, (t0)
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add t6, t6, a1
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slli a3, a1, 2
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add t0, t0, a3
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sub a4, a4, a1
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bnez a4, 5b
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// scalar horizontal pass (dx < 0, dy = 0)
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li a4, 3
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mv t0, sp
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mul a3, t4, a2
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add a3, a3, a0
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10:
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li a1, GRAIN_WIDTH - 3
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bge a4, a1, 13f
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lw a5, 0(t0)
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addi t0, t0, 4
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mv a6, t3
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li a1, 2
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mul a1, a1, t1
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addi a1, a1, 1
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mul a1, a1, t1
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add a6, a6, a1
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add a1, a3, a4
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sub a7, zero, t1
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11:
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bge a7, zero, 12f
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lb t5, 0(a6)
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addi a6, a6, 1
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add t6, a1, a7
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lb t6, 0(t6)
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mul t6, t6, t5
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add a5, a5, t6
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addi a7, a7, 1
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j 11b
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12:
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li a1, 1
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sll a1, a1, t2
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srai a1, a1, 1
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add a5, a5, a1
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sra a5, a5, t2
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add a1, a3, a4
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lb t5, 0(a1)
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add a5, a5, t5
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li t5, -128
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max a5, a5, t5
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li t5, 127
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min a5, a5, t5
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sb a5, 0(a1)
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addi a4, a4, 1
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j 10b
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13:
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addi t4, t4, 1
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j 4b
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14:
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addi sp, sp, 512
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15:
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ret
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endfunc
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@@ -0,0 +1,266 @@
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/*
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* Copyright © 2024, VideoLAN and dav1d authors
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* Copyright © 2024, Mohd Zaid
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "src/riscv/asm.S"
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#include "src/riscv/asm-offsets.h"
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#define GRAIN_WIDTH 82
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#define GRAIN_HEIGHT 73
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function generate_grain_y_16bpc_rvv, export=1, ext="v,zba,zbb"
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addi sp, sp, -32
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sd s0, 0(sp)
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sd s1, 8(sp)
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sd s2, 16(sp)
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// bitdepth scaling
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clzw t0, a2
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li t1, 24
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sub t0, t1, t0
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li t3, 128
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sll t3, t3, t0
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lbu t1, FGD_GRAIN_SCALE_SHIFT(a1)
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li t2, 4
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sub t2, t2, t0
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add t1, t1, t2
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sub s1, zero, t3
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addi s2, t3, -1
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lla a4, dav1d_gaussian_sequence
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lwu a5, FGD_SEED(a1)
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addi sp, sp, -256
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csrwi vxrm, 0
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li t2, GRAIN_HEIGHT
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0:
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li t3, GRAIN_WIDTH
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1:
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vsetvli t0, t3, e16, m8, ta, ma
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mv t6, t0
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mv a6, sp
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2:
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srliw t4, a5, 1
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xor t5, a5, t4
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srliw t4, a5, 3
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xor t5, t5, t4
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srliw t4, a5, 12
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xor t5, t5, t4
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andi t5, t5, 3
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srliw a5, a5, 2
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slli t5, t5, 14
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or a5, a5, t5
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srliw t4, a5, 4
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andi t4, t4, 2047
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slli t4, t4, 1
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srliw a7, a5, 5
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andi a7, a7, 2047
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slli a7, a7, 17
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or t4, t4, a7
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sw t4, 0(a6)
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addi a6, a6, 4
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addi t6, t6, -2
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bnez t6, 2b
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vsetvli zero, t0, e16, m8, ta, ma
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vle16.v v8, (sp)
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vloxei16.v v16, (a4), v8
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vssra.vx v8, v16, t1
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vse16.v v8, (a0)
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slli t4, t0, 1
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add a0, a0, t4
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sub t3, t3, t0
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bnez t3, 1b
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addi t2, t2, -1
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bnez t2, 0b
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addi sp, sp, 256
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// AR FILTER
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3:
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li t0, GRAIN_WIDTH * GRAIN_HEIGHT * 2
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sub a0, a0, t0
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lb t0, FGD_AR_COEFF_LAG(a1)
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beqz t0, 15f
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addi sp, sp, -512
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lbu t2, FGD_AR_COEFF_SHIFT(a1)
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addi t3, a1, FGD_AR_COEFFS_Y
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li t4, 3
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li a2, GRAIN_WIDTH
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4:
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li a4, GRAIN_HEIGHT
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bge t4, a4, 14f
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li a4, GRAIN_WIDTH - 6
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li t6, 3
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mv a6, sp
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5:
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vsetvli a7, a4, e16, m4, ta, ma
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vsetvli zero, zero, e32, m8, ta, ma
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vmv.v.i v24, 0
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sub a5, zero, t0
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mv s0, t3
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add a3, t4, a5
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mul a3, a3, a2
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add a3, a3, t6
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slli a3, a3, 1
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add a3, a3, a0
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vsetvli zero, zero, e16, m4, ta, ma
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6:
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bge a5, zero, 9f
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sub t1, zero, t0
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slli t1, t1, 1
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add a3, a3, t1
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sub t1, zero, t0
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7:
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bgt t1, t0, 8f
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lb t5, 0(s0)
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addi s0, s0, 1
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vle16.v v16, (a3)
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addi a3, a3, 2
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vwmacc.vx v24, t5, v16
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addi t1, t1, 1
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j 7b
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8:
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slli t1, a2, 1
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add a3, a3, t1
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slli t1, t0, 1
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sub a3, a3, t1
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addi a3, a3, -2
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addi a5, a5, 1
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j 6b
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9:
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vsetvli zero, a7, e32, m8, ta, ma
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vse32.v v24, (a6)
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add t6, t6, a7
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slli a3, a7, 2
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add a6, a6, a3
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sub a4, a4, a7
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bnez a4, 5b
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// scalar horizontal pass (dx < 0, dy = 0)
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li a4, 3
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mv a6, sp
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mul a3, t4, a2
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slli a3, a3, 1
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add a3, a3, a0
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10:
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li a7, GRAIN_WIDTH - 3
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bge a4, a7, 13f
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lw a5, 0(a6)
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addi a6, a6, 4
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mv s0, t3
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li a7, 2
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mul a7, a7, t0
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addi a7, a7, 1
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mul a7, a7, t0
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add s0, s0, a7
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slli t6, a4, 1
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add t6, a3, t6
|
||||
sub t1, zero, t0
|
||||
|
||||
11:
|
||||
bge t1, zero, 12f
|
||||
|
||||
lb t5, 0(s0)
|
||||
addi s0, s0, 1
|
||||
|
||||
slli a7, t1, 1
|
||||
add a7, t6, a7
|
||||
lh a7, 0(a7)
|
||||
mul a7, a7, t5
|
||||
add a5, a5, a7
|
||||
|
||||
addi t1, t1, 1
|
||||
j 11b
|
||||
|
||||
12:
|
||||
li a7, 1
|
||||
sll a7, a7, t2
|
||||
srai a7, a7, 1
|
||||
add a5, a5, a7
|
||||
sra a5, a5, t2
|
||||
|
||||
lh t5, 0(t6)
|
||||
add a5, a5, t5
|
||||
|
||||
max a5, a5, s1
|
||||
min a5, a5, s2
|
||||
|
||||
sh a5, 0(t6)
|
||||
addi a4, a4, 1
|
||||
j 10b
|
||||
|
||||
13:
|
||||
addi t4, t4, 1
|
||||
j 4b
|
||||
|
||||
14:
|
||||
addi sp, sp, 512
|
||||
15:
|
||||
ld s0, 0(sp)
|
||||
ld s1, 8(sp)
|
||||
ld s2, 16(sp)
|
||||
addi sp, sp, 32
|
||||
ret
|
||||
endfunc
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright © 2026, VideoLAN and dav1d authors
|
||||
* Copyright © 2026, Mohd Zaid
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef DAV1D_SRC_RISCV_64_ASM_OFFSETS_H
|
||||
#define DAV1D_SRC_RISCV_64_ASM_OFFSETS_H
|
||||
|
||||
#define FGD_SEED 0
|
||||
#define FGD_AR_COEFF_LAG 92
|
||||
#define FGD_AR_COEFFS_Y 96
|
||||
#define FGD_AR_COEFFS_UV 120
|
||||
#define FGD_AR_COEFF_SHIFT 176
|
||||
#define FGD_GRAIN_SCALE_SHIFT 184
|
||||
|
||||
#define FGD_SCALING_SHIFT 88
|
||||
#define FGD_UV_MULT 188
|
||||
#define FGD_UV_LUMA_MULT 196
|
||||
#define FGD_UV_OFFSET 204
|
||||
#define FGD_CLIP_TO_RESTRICTED_RANGE 216
|
||||
|
||||
#endif /*DAV1D_SRC_RISCV_64_ASM_OFFSETS_H*/
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright © 2026, VideoLAN and dav1d authors
|
||||
* Copyright © 2026, Mohd Zaid
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef DAV1D_SRC_RISCV_64_FILMGRAIN_H
|
||||
#define DAV1D_SRC_RISCV_64_FILMGRAIN_H
|
||||
|
||||
#include "src/cpu.h"
|
||||
#include "src/filmgrain.h"
|
||||
|
||||
decl_generate_grain_y_fn(BF(dav1d_generate_grain_y, rvv));
|
||||
|
||||
static ALWAYS_INLINE void film_grain_dsp_init_riscv(Dav1dFilmGrainDSPContext *const c){
|
||||
const unsigned flags = dav1d_get_cpu_flags();
|
||||
|
||||
if (!(flags & DAV1D_RISCV_CPU_FLAG_V)) return;
|
||||
|
||||
#if BITDEPTH == 8
|
||||
c->generate_grain_y = dav1d_generate_grain_y_8bpc_rvv;
|
||||
#elif BITDEPTH == 16
|
||||
c->generate_grain_y = dav1d_generate_grain_y_16bpc_rvv;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* DAV1D_SRC_RISCV_FILMGRAIN_H */
|
||||
Reference in New Issue
Block a user